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| Standard ICs 8-bit serial in, parallel out driver IC BU2050F The BU2050F is a driver IC that is comprised of an 8-bit shift register and a latch (serial in / parallel out). The data read into the shift register can be asynchronously latched. The CMOS outputs can provide 25mA (Max.) of current per output, making this IC ideal for a wide range of applications including driving LEDS. *Applications Printers, mini-component stereo systems, car audio systems, and musical instruments *Features of the clock and data input, the CLR pin 1) Regardless resets the latch circuit, and sets all outputs to the low level. 2) Output drive capacity: 25mA / output (Max.). 3) Input pin hysteresis: 0.5V (Typ.). *Block diagram VDD 14 P2 13 P1 12 CLR 11 STB 10 CLK 9 DATA 8 CTRL SHIFT REGISTER LATCH OUTPUT Driver 1 P3 2 P4 3 P5 4 VSS 5 P6 6 P7 7 P8 1 Standard ICs BU2050F *Pin descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 Pin name P3 P4 P5 VSS P6 P7 P8 DATA CLK STB Parallel data output Parallel data output Parallel data output GND Parallel data output Parallel data output Parallel data output Serial data input Clock signal input Strobe signal input When STB is low, the contents of the shift register are output. When STB is high, the contents of the latch circuit and output do not change. Reset signal input When CLR is low, the latch circuit is reset, and all outputs (P1 to P8) are set to low. Normally, CLR is high. Parallel data output Parallel data output Power supply voltage Function 11 12 13 14 CLR P1 P2 VDD *Absolute maximum ratings (Ta = 25C) Parameter Power supply voltage Input voltage output voltage Power dissipation1 Operating temperature Storage temperature Symbol VDD ISINK Vo Pd Topr Tstg Limits - 0.3 ~ + 7.0 VSS - 0.3 ~ VDD + 0.5 VSS - 0.3 ~ VDD + 0.5 450 - 25 ~ + 85 - 55 ~ + 125 Unit V mA V mW C C Note: These voltage value ranges are the destruction limits for the IC. They are not the guaranteed operating ranges for the IC. 1 Reduced by 4.5mW for each increase in Ta of 1C over 25C. *Input / output circuitsCLR (1) DATA, CLK, STB, (2) P1 ~ P8 2 Standard ICs BU2050F *Electrical characteristics (unless otherwise noted, VDD = 4.5V ~ 5.5V, Ta = 25C) Parameter Power supply current Input high level voltage Input low level voltage Input leak current Symbol IDD VIH VIL ILI Min. -- 0.7VDD VSS - 10 VDD - 1.5 Output high level voltage VOHD VDD - 1.0 VDD - 0.5 VSS Output low level voltage VOLD VSS VSS Typ. -- -- -- -- -- -- -- -- -- -- Max. 0.1 VDD 0.3VDD 10 VDD VDD VDD 1.5 0.8 0.4 Unit mA V V A V V V V V V V1 = 0 ~ VDD IOH = - 25mA IOH = - 15mA IOH = - 10mA IOL = + 25mA IOL = + 15mA IOL = + 10mA Conditions VIH = VDD, VIL = VSS -- -- *Switching characteristics (unless otherwise noted, VDD = 4.5V ~ 5.5V, Ta = 25C) Parameter Setup time (DATA-CLK) Hold time (DATA-CLK) Setup time (STB-CLK) Hold time (STB-CLK) Transmission delay time (CLK-P1 ~ P8) Transmission delay time (STB-P1 ~ P8) Transmission delay time (CLR-P1 ~ P8) Max. operating frequency Symbol tSD tHD tSSTB tHSTB tPDPCK tPDPSTB tPDPCLR fMAX Min. 20 20 30 30 -- -- -- 5 Typ. -- -- -- -- -- -- -- -- Max. -- -- -- -- 100 80 80 -- Unit ns ns ns ns ns ns ns MHz Conditions -- -- -- -- -- -- -- -- 3 Standard ICs BU2050F *Switching characteristics f MAX CLK 1 2 8 9 10 11 12 t SD DATA t HD STB t HSTB CLR t SSTB P8 t PDPST P1 t PDPCR t PDPCK 4 Standard ICs BU2050F *Timing chart CLK CLR STB DATA P1 P2 P3 P4 P5 P6 P7 P8 *Circuitisoperation of an 8-bit shift register, a latch, and This IC made up an output driver. The four input pins (data (DATA), strobe (STB), latch reset (CLR), and ckock (CLK)) are all hysteresis inputs (0.5V Typ.). The reset function applies to all bits in the latch circuit. When CLR is low, the latch circuit is reset asynchronously, regardless of the other inputs, and all outputs are set to low. The CLR pin is normally high. The serial data input to the data pin is synchronously read into the shift register on the rising edge of the clock. When STB is low (CLR is high), the data in the shift register is transferred to the latch circuit, and output on the parallel data output pins (P1 ~ P8). When STB is high, the latch circuit and output data does not change. 5 Standard ICs BU2050F *Electrical characteristic curves OUTPUT CURRENT "HIGH" LEVEL: IOH (mA) OUTPUT CURRENT "LOW" LEVEL: IOL (mA) 600 POWER DISSIPATION: Pd (mw) 500 400 300 200 100 0 0 25 50 75 100 125 150 AMBIENT TEMPERATURE: Ta (C) 30 25 20 15 10 5 0 4.2 30 25 20 15 VDD = 5V 10 5 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 OUTPUT VOLTAGE "LOW" LEVEL: VOL (V) 4.3 4.4 4.5 4.6 4.7 4.8 4.9 5 OUTPUT VOLTAGE "HIGH" LEVEL: VOH (V) Fig. 1 Thermal derating characteristics Fig. 2 Output high level current vs. output high level voltage Fig. 3 Output low level current vs. output low level voltage *External dimensions (Units: mm) 8.7 0.2 14 6.2 0.3 4.4 0.2 8 1.5 0.1 1 7 0.11 1.27 0.4 0.1 0.3Min. 0.15 SOP14 6 0.15 0.1 |
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